The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure containing replacement metal gate structures having low resistance and a method of forming the same.
Current complementary metal oxide semiconductor (CMOS) technology relies on a replacement metal gate process flow for fabricating n-type field effect transistors (nFETs) and p-type field effect transistors (pFETs). In such a process, a first workfunction metal layer is used in providing the replacement gate of the nFET, while a second workfunction metal layer, different from the first workfunction metal layer, is used in providing the replacement metal gate for the pFET.
The use of two different workfunction metal layers in providing the replacement metal gates for the nFET and pFET significantly impacts performance since integration of two workfunction metal layers leaves very little room for the gate conductors. Furthermore, aggressive scaling requires narrow gates which have very high gate resistance due to poor metal fill. Hence, there exists a need to solve the high gate resistance problem to ensure continuous scaling.